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Change DCSR bits to match spec.
[riscv-isa-sim.git]
/
Makefile.in
diff --git
a/Makefile.in
b/Makefile.in
index 5f0102a2ada51ba84730f6d9e58652b26d415eb3..2eb7bfd0443827ed903b902aa7c1034b66652109 100644
(file)
--- a/
Makefile.in
+++ b/
Makefile.in
@@
-121,7
+121,8
@@
INSTALL_EXE := $(INSTALL) -m 555
STOW := @stow@
# Tests
-bintests = tests/gdbserver.py
+bintests = tests/gdbserver.py \
+ tests/ebreak.py
#-------------------------------------------------------------------------
# Include subproject makefile fragments