if (cause == CAUSE_ILLEGAL_INSTRUCTION)
exit(0); // no PMP support
- if (!trap_expected)
+ if (!trap_expected || cause != CAUSE_LOAD_ACCESS)
exit(1);
trap_expected = 0;
return epc + insn_len(epc);
l3pt[SCRATCH / RISCV_PGSIZE] = ((uintptr_t)scratch >> RISCV_PGSHIFT << PTE_PPN_SHIFT) | PTE_A | PTE_D | PTE_V | PTE_R | PTE_W;
#if __riscv_xlen == 64
l2pt[0] = ((uintptr_t)l3pt >> RISCV_PGSHIFT << PTE_PPN_SHIFT) | PTE_V;
- uintptr_t vm_choice = SPTBR_MODE_SV39;
+ uintptr_t vm_choice = SATP_MODE_SV39;
#else
- uintptr_t vm_choice = SPTBR_MODE_SV32;
+ uintptr_t vm_choice = SATP_MODE_SV32;
#endif
write_csr(sptbr, ((uintptr_t)l1pt >> RISCV_PGSHIFT) |
- (vm_choice * (SPTBR_MODE & ~(SPTBR_MODE<<1))));
- write_csr(pmpcfg0, (PMP_EN | PMP_NAPOT | PMP_R) << 16);
+ (vm_choice * (SATP_MODE & ~(SATP_MODE<<1))));
+ write_csr(pmpcfg0, (PMP_NAPOT | PMP_R) << 16);
write_csr(pmpaddr2, -1);
}
INLINE int pmp_ok(pmpcfg_t p, uintptr_t addr, uintptr_t size)
{
- if (!(p.cfg & PMP_TOR)) {
+ if ((p.cfg & PMP_A) == 0)
+ return 1;
+
+ if ((p.cfg & PMP_A) != PMP_TOR) {
uintptr_t range = 1;
- if (p.cfg & PMP_NAPOT) {
+ if ((p.cfg & PMP_A) == PMP_NAPOT) {
range <<= 1;
for (uintptr_t i = 1; i; i <<= 1) {
if ((p.a1 & i) == 0)
write_csr(pmpaddr0, p.a0);
write_csr(pmpaddr1, p.a1);
write_csr(pmpcfg0, ((p.cfg << 8) & 0xff00) | (cfg0 & ~0xff00));
- asm volatile ("sfence.vma");
+ asm volatile ("sfence.vma" ::: "memory");
return p;
}
INLINE pmpcfg_t set_pmp_range(uintptr_t base, uintptr_t range)
{
pmpcfg_t p;
- p.cfg = PMP_EN | PMP_TOR | PMP_M | PMP_R;
+ p.cfg = PMP_TOR | PMP_R;
p.a0 = base >> PMP_SHIFT;
p.a1 = (base + range) >> PMP_SHIFT;
return set_pmp(p);
INLINE pmpcfg_t set_pmp_napot(uintptr_t base, uintptr_t range)
{
pmpcfg_t p;
- p.cfg = PMP_EN | PMP_M | PMP_R | (range > GRANULE ? PMP_NAPOT : 0);
+ p.cfg = PMP_R | (range > GRANULE ? PMP_NAPOT : PMP_NA4);
p.a0 = 0;
p.a1 = (base + (range/2 - 1)) >> PMP_SHIFT;
return set_pmp(p);