On misaligned fetch, set EPC to target, not branch itself

[riscv-isa-sim.git] / config.h.in

diff --git a/config.h.in b/config.h.in
index 42d4d223a41cbbdf88a2fcae8e83f8ebb50520c3..52c725334ffdea85adc4ba99a916becf33cd8e7c 100644 (file)
--- a/config.h.in
+++ b/config.h.in
@@ -1,7 +1,7 @@
 /* config.h.in.  Generated from configure.ac by autoheader.  */
 
-/* Define to 1 if you have the `dl' library (-ldl). */
-#undef HAVE_LIBDL
+/* Define if subproject MCPPBS_SPROJ_NORM is enabled */
+#undef DUMMY_ROCC_ENABLED
 
 /* Define to 1 if you have the `fesvr' library (-lfesvr). */
 #undef HAVE_LIBFESVR
@@ -49,7 +49,7 @@
 #undef SOFTFLOAT_ENABLED
 
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
-#undef SPIKE_ENABLED
+#undef SPIKE_MAIN_ENABLED
 
 /* Define to 1 if you have the ANSI C header files. */
 #undef STDC_HEADERS