self.comb += self.get_csr_op_is_valid(csr_op_is_valid, csr_number,
csr_reads, csr_writes)
+ # TODO
+ cycle_counter = Signal(64); # TODO: implement cycle_counter
+ time_counter = Signal(64); # TODO: implement time_counter
+ instret_counter = Signal(64); # TODO: implement instret_counter
+
if __name__ == "__main__":
example = CPU()
print(verilog.convert(example,