Merge pull request #47 from riscv/debug-0.13

[riscv-tests.git] / debug / README.md

diff --git a/debug/README.md b/debug/README.md
index 4a90c0c770aad9157da31f720ef60d689d141639..04aa13a969d7304bc1d0d968063c61bf5f65a051 100644 (file)
--- a/debug/README.md
+++ b/debug/README.md
@@ -2,9 +2,9 @@ Debug Tests
 ===========
 
 Debugging requires many system components to all work together. The tests here
-perform an end-to-end test, communicating only with gdb. If a simulator or
-hardware passes all these tests, then you can be pretty confident that the
-actual debug interface is functioning correctly.
+perform an end-to-end test, communicating with gdb and OpenOCD.
+If a simulator or hardware passes all these tests, then you can be pretty
+confident that the actual debug interface is functioning correctly.
 
 Targets
 =======
@@ -19,10 +19,17 @@ Targets
 
 `./gdbserver.py --spike32 --cmd $RISCV/bin/spike`
 
-32-bit SiFive Core on Arty FPGA board
+32-bit SiFive Core on Supported FPGA Boards &  Hardware
 -------------------------------------
 
 `./gdbserver.py --freedom-e300`
+`./gdbserver.py --hifive1`
+
+
+32-bit rocket-chip core in Simulation
+-------------------------------------
+
+`./gdbserver.py --freedom-e300-sim`
 
 Debug Tips
 ==========