Let Spike have the default amount of RAM

[riscv-tests.git] / debug / gdbserver.py

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 6690ad92c85f1dfbe6fbc9c614a073478253acac..029439ea04992918ffaee706947537a4b69c7f74 100755 (executable)
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -80,6 +80,8 @@ class SimpleRegisterTest(GdbTest):
         self.gdb.command("p *((int*) 0x%x)=0x13" % self.target.ram)
         self.gdb.command("p *((int*) 0x%x)=0x13" % (self.target.ram + 4))
         self.gdb.command("p *((int*) 0x%x)=0x13" % (self.target.ram + 8))
+        self.gdb.command("p *((int*) 0x%x)=0x13" % (self.target.ram + 12))
+        self.gdb.command("p *((int*) 0x%x)=0x13" % (self.target.ram + 16))
         self.gdb.p("$pc=0x%x" % self.target.ram)
 
 class SimpleS0Test(SimpleRegisterTest):
@@ -100,6 +102,8 @@ class SimpleT1Test(SimpleRegisterTest):
 
 class SimpleF18Test(SimpleRegisterTest):
     def check_reg(self, name):
+        self.gdb.p_raw("$mstatus=$mstatus | 0x00006000")
+        self.gdb.stepi()
         a = random.random()
         b = random.random()
         self.gdb.p_raw("$%s=%f" % (name, a))
@@ -678,7 +682,7 @@ def main():
             epilog="""
             Example command line from the real world:
             Run all RegsTest cases against a physical FPGA, with custom openocd command:
-            ./gdbserver.py --freedom-e300 --cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" Simple
+            ./gdbserver.py --freedom-e300 --server_cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" Simple
             """)
     targets.add_target_options(parser)
 
@@ -688,7 +692,7 @@ def main():
     global parsed   # pylint: disable=global-statement
     parsed = parser.parse_args()
 
-    target = parsed.target(parsed.cmd, parsed.run, parsed.isolate)
+    target = parsed.target(parsed.server_cmd, parsed.sim_cmd, parsed.isolate)
     if parsed.xlen:
         target.xlen = parsed.xlen