Ensure there are no unnamed registers.

[riscv-tests.git] / debug / gdbserver.py

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index f2c84ae1b9b0670411c4259fb0b7711ec70dbc4d..521fffbf82ec59304f64d5df9fba502a25814f47 100755 (executable)
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -396,6 +396,8 @@ class Registers(DebugTest):
             output = self.gdb.command(cmd)
             for reg in ('zero', 'ra', 'sp', 'gp', 'tp'):
                 assertIn(reg, output)
+            for line in output.splitlines():
+                assertRegexpMatches(line, r"^\S")
 
         #TODO
         # mcpuid is one of the few registers that should have the high bit set
@@ -814,6 +816,14 @@ class PrivTest(GdbTest):
 class PrivRw(PrivTest):
     def test(self):
         """Test reading/writing priv."""
+        # Disable physical memory protection by allowing U mode access to all
+        # memory.
+        self.gdb.p("$pmpcfg0=0xf")  # TOR, R, W, X
+        self.gdb.p("$pmpaddr0=0x%x" %
+                ((self.hart.ram + self.hart.ram_size) >> 2))
+
+        # Leave the PC at _start, where the first 4 instructions should be
+        # legal in any mode.
         for privilege in range(4):
             self.gdb.p("$priv=%d" % privilege)
             self.gdb.stepi()
@@ -862,9 +872,7 @@ def main():
     global parsed   # pylint: disable=global-statement
     parsed = parser.parse_args()
     target = targets.target(parsed)
-
-    if parsed.xlen:
-        target.xlen = parsed.xlen
+    testlib.print_log_names = parsed.print_log_names
 
     module = sys.modules[__name__]