Add back code to clean up triggers in entry.S

[riscv-tests.git] / debug / programs / entry.S

diff --git a/debug/programs/entry.S b/debug/programs/entry.S
index e021860f58c38b85b703e6992aa6488f01e7aaed..ff8ae3092a517ad20ce2860b7b56ac2d1cd05b5a 100755 (executable)
--- a/debug/programs/entry.S
+++ b/debug/programs/entry.S
@@ -27,12 +27,33 @@ trap_vector:
   j trap_entry
 
 handle_reset:
-  la t0, trap_entry
+  // If misa doesn't exist (or is following an old spec where it has a
+  // different number), skip the next block.
+  la t0, 3f
   csrw mtvec, t0
   csrwi mstatus, 0
+
+  // make sure these registers exist by seeing if either S or U bits
+  // are set before attempting to zero them out.
+  csrr   t1, misa
+  addi   t2, x0, 1     
+  slli   t2, t2, 20 // U_EXTENSION
+  and    t2, t1, t2
+  bne    x0, t2, 1f
+  addi   t2, x0, 1
+  slli   t2, t2, 18 // S_EXTENSION     
+  and    t2, t1, t2
+  bne    x0, t2, 1f
+  j 2f
+1:
   csrwi mideleg, 0
   csrwi medeleg, 0
+2:
   csrwi mie, 0
+3:
+  la t0, trap_entry
+  csrw mtvec, t0
+  csrwi mstatus, 0
 
   # initialize global pointer
 .option push