Add tests for virtual priv register.

[riscv-tests.git] / debug / programs / mprv.S

diff --git a/debug/programs/mprv.S b/debug/programs/mprv.S
index df346b3504ddc291ed3282424b2a0278c9a64f5f..115ccb5b9fead1537d37f83fdaf62119c9bc1f19 100644 (file)
--- a/debug/programs/mprv.S
+++ b/debug/programs/mprv.S
@@ -1,10 +1,10 @@
-#include "../riscv/encoding.h"
+#include "../../env/encoding.h"
 #define PGSHIFT         12
 
-        .global         _start
+        .global         main
 
         .section        .text
-_start:
+main:
         # Set up a page table entry that maps 0x0... to 0x8...
         la      t0, page_table
         srli    t0, t0, PGSHIFT
@@ -12,7 +12,11 @@ _start:
 
         # update mstatus
         csrr    t1, CSR_MSTATUS
+#ifdef __riscv32
+        li      t0, (MSTATUS_MPRV | (VM_SV32 << 24))
+#else
         li      t0, (MSTATUS_MPRV | (VM_SV39 << 24))
+#endif
         #li      t0, ((VM_SV39 << 24))
         or      t1, t0, t1
         csrw    CSR_MSTATUS, t1
@@ -34,5 +38,9 @@ data:
 
         .balign 0x1000
 page_table:
-        .word   ((0x80000000 >> 2) | PTE_V | PTE_TYPE_URWX_SRWX)
+#ifdef __riscv32
+        .word   ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U)
+#else
+        .word   ((0x80000000 >> 2) | PTE_V | PTE_R | PTE_W | PTE_X | PTE_G | PTE_U)
         .word   0
+#endif