projects / riscv-tests.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
Add tests for virtual priv register.
[riscv-tests.git] / debug / programs / priv.S
diff --git a/debug/programs/priv.S b/debug/programs/priv.S
new file mode 100644 (file)
index 0000000..2d20a65
--- /dev/null
+++ b/debug/programs/priv.S
@@ -0,0 +1,11 @@
+#include "../../env/encoding.h"
+
+        .global         main
+
+        .section        .text
+main:
+        # MISA is only readable from machine mode
+        csrr    t0, CSR_MISA
+        csrr    t0, CSR_MISA
+        csrr    t0, CSR_MISA
+        csrr    t0, CSR_MISA