use_fpu = False
misa = None
- def __init__(self, cmd, run, isolate):
- self.cmd = cmd
- self.run = run
+ def __init__(self, server_cmd, sim_cmd, isolate):
+ self.server_cmd = server_cmd
+ self.sim_cmd = sim_cmd
self.isolate = isolate
def target(self):
def server(self):
"""Start the debug server that gdb connects to, eg. OpenOCD."""
if self.openocd_config:
- return testlib.Openocd(cmd=self.cmd, config=self.openocd_config)
+ return testlib.Openocd(server_cmd=self.server_cmd,
+ config=self.openocd_config)
else:
raise NotImplementedError
def extensionSupported(self, letter):
# target.misa is set by testlib.ExamineTarget
- return self.misa & (1 << (ord(letter.upper()) - ord('A')))
+ if self.misa:
+ return self.misa & (1 << (ord(letter.upper()) - ord('A')))
+ else:
+ return False
class SpikeTarget(Target):
# pylint: disable=abstract-method
- directory = "spike"
- ram = 0x80010000
- ram_size = 5 * 1024 * 1024
instruction_hardware_breakpoint_count = 4
reset_vector = 0x1000
class Spike64Target(SpikeTarget):
name = "spike64"
+ directory = name
xlen = 64
use_fpu = True
+ # Would like to use 0x7fffffffffff0000 because it crosses the 0x8000...
+ # boundary, but spike doesn't support that in the code where it generates
+ # the reset vector.
+ ram = 0x1212340000
+ ram_size = 0x10000000
+ openocd_config = "targets/%s/openocd.cfg" % directory
- def server(self):
- return testlib.Spike(self.cmd, halted=True)
+ def target(self):
+ return testlib.Spike(self)
class Spike32Target(SpikeTarget):
name = "spike32"
+ directory = name
xlen = 32
+ ram = 0x10000000
+ ram_size = 0x10000000
+ openocd_config = "targets/%s/openocd.cfg" % directory
- def server(self):
- return testlib.Spike(self.cmd, halted=True, xlen=32)
+ def target(self):
+ return testlib.Spike(self)
class FreedomE300Target(Target):
name = "freedom-e300"
instruction_hardware_breakpoint_count = 2
openocd_config = "targets/%s/openocd.cfg" % name
+class HiFive1Target(FreedomE300Target):
+ name = "HiFive1"
+ openocd_config = "targets/%s/openocd.cfg" % name
+
class FreedomE300SimTarget(Target):
name = "freedom-e300-sim"
xlen = 32
- timeout_sec = 240
+ timeout_sec = 6000
ram = 0x80000000
ram_size = 256 * 1024 * 1024
instruction_hardware_breakpoint_count = 2
openocd_config = "targets/%s/openocd.cfg" % name
def target(self):
- return testlib.VcsSim(simv=self.run, debug=False)
+ return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
class FreedomU500Target(Target):
name = "freedom-u500"
class FreedomU500SimTarget(Target):
name = "freedom-u500-sim"
xlen = 64
- timeout_sec = 240
+ timeout_sec = 6000
ram = 0x80000000
ram_size = 256 * 1024 * 1024
instruction_hardware_breakpoint_count = 2
openocd_config = "targets/%s/openocd.cfg" % name
def target(self):
- return testlib.VcsSim(simv=self.run, debug=False)
+ return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
targets = [
Spike32Target,
FreedomE300Target,
FreedomU500Target,
FreedomE300SimTarget,
- FreedomU500SimTarget]
+ FreedomU500SimTarget,
+ HiFive1Target]
def add_target_options(parser):
group = parser.add_mutually_exclusive_group(required=True)
for t in targets:
group.add_argument("--%s" % t.name, action="store_const", const=t,
dest="target")
- parser.add_argument("--run",
+ parser.add_argument("--sim_cmd",
help="The command to use to start the actual target (e.g. "
"simulation)")
- parser.add_argument("--cmd",
- help="The command to use to start the debug server.")
+ parser.add_argument("--server_cmd",
+ help="The command to use to start the debug server (e.g. OpenOCD)")
xlen_group = parser.add_mutually_exclusive_group()
xlen_group.add_argument("--32", action="store_const", const=32, dest="xlen",