Don't rely on Spike's default ISA

[riscv-tests.git] / debug / testlib.py

diff --git a/debug/testlib.py b/debug/testlib.py
index a66d59a7b450baf63e7b99aa6c50ef6e0ded3fec..c39ed517a879576286dc758c153f9a97829b6f1f 100644 (file)
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -67,7 +67,9 @@ class Spike(object):
             spike = os.path.expandvars("$RISCV/bin/spike")
             cmd = [spike]
         if xlen == 32:
-            cmd += ["--isa", "RV32"]
+            cmd += ["--isa", "RV32G"]
+        else:
+            cmd += ["--isa", "RV64G"]
 
         if timeout:
             cmd = ["timeout", str(timeout)] + cmd
@@ -77,7 +79,6 @@ class Spike(object):
         if with_jtag_gdb:
             cmd += ['--rbb-port', '0']
             os.environ['REMOTE_BITBANG_HOST'] = 'localhost'
-        cmd.append("-m32")
         cmd.append('programs/infinite_loop')
         if binary:
             cmd.append(binary)
@@ -113,7 +114,7 @@ class Spike(object):
 class VcsSim(object):
     def __init__(self, sim_cmd=None, debug=False):
         if sim_cmd:
-            cmd = shlex.split(simv)
+            cmd = shlex.split(sim_cmd)
         else:
             cmd = ["simv"]
         cmd += ["+jtag_vpi_enable"]