Abstract register read mostly working.

[riscv-isa-sim.git] / debug_rom / debug_rom.S

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index c164eeb268d4c753af3605d9f8efb5c23e4f7178..74a934b201a94a31be63b24dd7c68a1149dcdecc 100755 (executable)
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -5,18 +5,19 @@
 
 # TODO: Update these constants once they're finalized in the doc.
 
-#define DCSR                    0x790
-#define DCSR_CAUSE_DEBINT       3
-#define DCSR_HALT_OFFSET        3
-#define DCSR_DEBUGINT_OFFSET    10
-
-#define DSCRATCH                0x792
-
 #define DEBUG_RAM               0x400
-#define DEBUG_RAM_SIZE          64
+#ifndef DEBUG_RAM_SIZE
+# define DEBUG_RAM_SIZE          64
+#endif
 
-#define SETHALTNOT              0x100
-#define CLEARDEBINT             0x108
+#define CLEARDEBINT             0x100
+#define SETHALTNOT              0x10c
+
+#if (defined(RV32) + defined(RV64) + defined(RV128)) > 1
+# define MULTI_XLEN
+#elif (defined(RV32) + defined(RV64) + defined(RV128)) == 0
+# error define one or more of RV32, RV64, RV128
+#endif
 
         .global entry
         .global resume
@@ -37,80 +38,115 @@ exception:
 _resume:
         li      s0, 0
 _resume2:
-        # Clear debug interrupt.
-        csrr    s1, CSR_MHARTID
-        sw      s1, CLEARDEBINT(zero)
         fence
 
         # Restore s1.
+#ifdef MULTI_XLEN
         csrr    s1, CSR_MISA
+#endif
+
+#ifdef RV32
+# ifdef MULTI_XLEN
         bltz    s1, restore_not_32
+# endif
+
 restore_32:
         lw      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
-        j       check_halt
+# if defined(RV64) || defined(RV128)
+        j       finish_restore
+# endif
+#endif
+
 restore_not_32:
+#if defined(RV64) && defined(RV128)
         slli    s1, s1, 1
         bltz    s1, restore_128
+#endif
+
+#ifdef RV64
 restore_64:
         ld      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
-        j       check_halt
+#endif
+#if defined(RV64) && defined(RV128)
+        j       finish_restore
+#endif
+#ifdef RV128
 restore_128:
-        nop     #lq      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
+        lq      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
+#endif
 
+finish_restore:
         # s0 contains ~0 if we got here through an exception, and 0 otherwise.
         # Store this to the last word in Debug RAM so the debugger can tell if
         # an exception occurred.
         sw      s0, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
 
+        # Clear debug interrupt.
+        csrr    s0, CSR_MHARTID
+        sw      s0, CLEARDEBINT(zero)
+
 check_halt:
-        csrr    s0, DCSR
-        andi    s0, s0, (1<<DCSR_HALT_OFFSET)
-        beqz    s0, exit
-        j       wait_for_interrupt
+        csrr    s0, CSR_DCSR
+        andi    s0, s0, DCSR_HALT
+        bnez    s0, wait_for_interrupt
 
 exit:
         # Restore s0.
-        csrr    s0, DSCRATCH
+        csrr    s0, CSR_DSCRATCH
         dret
 
-
 _entry:
         # Save s0 in DSCRATCH
-        csrw    DSCRATCH, s0
+        csrw    CSR_DSCRATCH, s0
 
         # Check why we're here
-        csrr    s0, DCSR
-        # cause is in bits 2:0 of dcsr
-        andi    s0, s0, 7
-        addi    s0, s0, -DCSR_CAUSE_DEBINT
+        csrr    s0, CSR_DCSR
+        # cause is in bits 8:6 of dcsr
+        andi    s0, s0, DCSR_CAUSE
+        addi    s0, s0, -(DCSR_CAUSE_DEBUGINT<<6)
         bnez    s0, spontaneous_halt
 
 jdebugram:
         # Save s1 so that the debug program can use two registers.
-        fence.i
+#ifdef MULTI_XLEN
         csrr    s0, CSR_MISA
+#endif
+
+#ifdef RV32
+# ifdef MULTI_XLEN
         bltz    s0, save_not_32
+# endif
 save_32:
         sw      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
         jr      zero, DEBUG_RAM
+#endif
+
 save_not_32:
+#if defined(RV64) && defined(RV128)
         slli    s0, s0, 1
         bltz    s0, save_128
+#endif
+
+#ifdef RV64
 save_64:
         sd      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
         jr      zero, DEBUG_RAM
+#endif
+
+#ifdef RV128
 save_128:
-        nop     #sq      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
+        sq      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
         jr      zero, DEBUG_RAM
+#endif
 
 spontaneous_halt:
         csrr    s0, CSR_MHARTID
         sw      s0, SETHALTNOT(zero)
-        csrsi   DCSR, (1<<DCSR_HALT_OFFSET)
+        csrsi   CSR_DCSR, DCSR_HALT
 
 wait_for_interrupt:
-        csrr    s0, DCSR
-        andi    s0, s0, (1<<DCSR_DEBUGINT_OFFSET)
+        csrr    s0, CSR_DCSR
+        andi    s0, s0, DCSR_DEBUGINT
         beqz    s0, wait_for_interrupt
 
         j       jdebugram