Move cleardebint, per spec.

[riscv-isa-sim.git] / debug_rom / debug_rom.S

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index 7130364b8f7ba163cd7d575eedba64491b14cfe9..e7547a0353e415169fed4181a5571d13f81fe121 100755 (executable)
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -5,37 +5,35 @@
 
 # TODO: Update these constants once they're finalized in the doc.
 
-#define DCSR                    0x790
-#define DCSR_CAUSE_DEBINT       3
-#define DCSR_HALT_OFFSET        3
-#define DCSR_DEBUGINT_OFFSET    10
-
-#define DSCRATCH                0x792
-
-# TODO: Should be 0x400
-#define DEBUG_RAM               (-0x400)
+#define DEBUG_RAM               0x400
 #define DEBUG_RAM_SIZE          64
 
-# TODO: Should be 0x100, 0x108
-#define SETHALTNOT              (-0x100)
-#define CLEARDEBINT             (-0x108)
+#define SETHALTNOT              0x100
+#define CLEARDEBINT             0x104
 
         .global entry
         .global resume
+        .global exception
 
         # Automatically called when Debug Mode is first entered.
 entry:  j       _entry
         # Should be called by Debug RAM code that has finished execution and
         # wants to return to Debug Mode.
 resume:
+        j       _resume
+exception:
+        # Set the last word of Debug RAM to all ones, to indicate that we hit
+        # an exception.
+        li      s0, ~0
+        j       _resume2
+
+_resume:
+        li      s0, 0
+_resume2:
         # Clear debug interrupt.
-clear_debint:
         csrr    s1, CSR_MHARTID
         sw      s1, CLEARDEBINT(zero)
-clear_debint_loop:
-        csrr    s1, DCSR
-        andi    s1, s1, (1<<DCSR_DEBUGINT_OFFSET)
-        bnez    s1, clear_debint_loop
+        fence
 
         # Restore s1.
         csrr    s1, CSR_MISA
@@ -52,31 +50,36 @@ restore_64:
 restore_128:
         nop     #lq      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
 
+        # s0 contains ~0 if we got here through an exception, and 0 otherwise.
+        # Store this to the last word in Debug RAM so the debugger can tell if
+        # an exception occurred.
+        sw      s0, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
+
 check_halt:
-        csrr    s0, DCSR
-        andi    s0, s0, (1<<DCSR_HALT_OFFSET)
+        csrr    s0, CSR_DCSR
+        andi    s0, s0, DCSR_HALT
         beqz    s0, exit
         j       wait_for_interrupt
 
 exit:
         # Restore s0.
-        csrr    s0, DSCRATCH
-        eret
-
+        csrr    s0, CSR_DSCRATCH
+        .word   0x79200073      # TODO: dret
 
 _entry:
         # Save s0 in DSCRATCH
-        csrw    DSCRATCH, s0
+        csrw    CSR_DSCRATCH, s0
 
         # Check why we're here
-        csrr    s0, DCSR
+        csrr    s0, CSR_DCSR
         # cause is in bits 2:0 of dcsr
-        andi    s0, s0, 7
-        addi    s0, s0, -DCSR_CAUSE_DEBINT
+        andi    s0, s0, DCSR_CAUSE
+        addi    s0, s0, -DCSR_CAUSE_DEBUGINT
         bnez    s0, spontaneous_halt
 
 jdebugram:
         # Save s1 so that the debug program can use two registers.
+        fence.i
         csrr    s0, CSR_MISA
         bltz    s0, save_not_32
 save_32:
@@ -95,11 +98,11 @@ save_128:
 spontaneous_halt:
         csrr    s0, CSR_MHARTID
         sw      s0, SETHALTNOT(zero)
-        csrsi   DCSR, DCSR_HALT_OFFSET
+        csrsi   CSR_DCSR, DCSR_HALT
 
 wait_for_interrupt:
-        csrr    s0, DCSR
-        andi    s0, s0, (1<<DCSR_DEBUGINT_OFFSET)
+        csrr    s0, CSR_DCSR
+        andi    s0, s0, DCSR_DEBUGINT
         beqz    s0, wait_for_interrupt
 
         j       jdebugram