Move cleardebint, per spec.

[riscv-isa-sim.git] / debug_rom / debug_rom.S

diff --git a/debug_rom/debug_rom.S b/debug_rom/debug_rom.S
index b1fa8bd702d6fa4a15a1c0b3330420c4acb615a6..e7547a0353e415169fed4181a5571d13f81fe121 100755 (executable)
--- a/debug_rom/debug_rom.S
+++ b/debug_rom/debug_rom.S
@@ -5,18 +5,11 @@
 
 # TODO: Update these constants once they're finalized in the doc.
 
-#define DCSR                    0x790
-#define DCSR_CAUSE_DEBINT       3
-#define DCSR_HALT_OFFSET        3
-#define DCSR_DEBUGINT_OFFSET    10
-
-#define DSCRATCH                0x792
-
 #define DEBUG_RAM               0x400
 #define DEBUG_RAM_SIZE          64
 
 #define SETHALTNOT              0x100
-#define CLEARDEBINT             0x108
+#define CLEARDEBINT             0x104
 
         .global entry
         .global resume
@@ -29,15 +22,14 @@ entry:  j       _entry
 resume:
         j       _resume
 exception:
-        # Flip the LSB of the first word in Debug RAM so the debugger can know
-        # that we hit an exception.
-        lw      s1, (DEBUG_RAM)(zero)
-        xori    s1, s1, 1
-        sw      s1, (DEBUG_RAM)(zero)
-
-        # Fall through to resume.
+        # Set the last word of Debug RAM to all ones, to indicate that we hit
+        # an exception.
+        li      s0, ~0
+        j       _resume2
 
 _resume:
+        li      s0, 0
+_resume2:
         # Clear debug interrupt.
         csrr    s1, CSR_MHARTID
         sw      s1, CLEARDEBINT(zero)
@@ -58,32 +50,36 @@ restore_64:
 restore_128:
         nop     #lq      s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
 
+        # s0 contains ~0 if we got here through an exception, and 0 otherwise.
+        # Store this to the last word in Debug RAM so the debugger can tell if
+        # an exception occurred.
+        sw      s0, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
+
 check_halt:
-        csrr    s0, DCSR
-        andi    s0, s0, (1<<DCSR_HALT_OFFSET)
+        csrr    s0, CSR_DCSR
+        andi    s0, s0, DCSR_HALT
         beqz    s0, exit
         j       wait_for_interrupt
 
 exit:
         # Restore s0.
-        csrr    s0, DSCRATCH
-        # TODO: dret?
-        mret
-
+        csrr    s0, CSR_DSCRATCH
+        .word   0x79200073      # TODO: dret
 
 _entry:
         # Save s0 in DSCRATCH
-        csrw    DSCRATCH, s0
+        csrw    CSR_DSCRATCH, s0
 
         # Check why we're here
-        csrr    s0, DCSR
+        csrr    s0, CSR_DCSR
         # cause is in bits 2:0 of dcsr
-        andi    s0, s0, 7
-        addi    s0, s0, -DCSR_CAUSE_DEBINT
+        andi    s0, s0, DCSR_CAUSE
+        addi    s0, s0, -DCSR_CAUSE_DEBUGINT
         bnez    s0, spontaneous_halt
 
 jdebugram:
         # Save s1 so that the debug program can use two registers.
+        fence.i
         csrr    s0, CSR_MISA
         bltz    s0, save_not_32
 save_32:
@@ -102,11 +98,11 @@ save_128:
 spontaneous_halt:
         csrr    s0, CSR_MHARTID
         sw      s0, SETHALTNOT(zero)
-        csrsi   DCSR, (1<<DCSR_HALT_OFFSET)
+        csrsi   CSR_DCSR, DCSR_HALT
 
 wait_for_interrupt:
-        csrr    s0, DCSR
-        andi    s0, s0, (1<<DCSR_DEBUGINT_OFFSET)
+        csrr    s0, CSR_DCSR
+        andi    s0, s0, DCSR_DEBUGINT
         beqz    s0, wait_for_interrupt
 
         j       jdebugram