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Abstract register read mostly working.
[riscv-isa-sim.git]
/
debug_rom
/
link.ld
diff --git
a/debug_rom/link.ld
b/debug_rom/link.ld
index 356099c682171ba1d5aa6152706399f198fdf87a..aba6ae802e13f23a2c8edaf656f8535255a0fd53 100644
(file)
--- a/
debug_rom/link.ld
+++ b/
debug_rom/link.ld
@@
-2,7
+2,7
@@
OUTPUT_ARCH( "riscv" )
ENTRY( entry )
SECTIONS
{
- . = 0x
fffff800; /* TODO: 0x800 */
+ . = 0x
800;
.text :
{
*(.text)