Use new NaN discipline

[riscv-isa-sim.git] / hwacha / hwacha.cc

diff --git a/hwacha/hwacha.cc b/hwacha/hwacha.cc
index fdd215eb1d884e00db8dff4d9f25cdfa1b172457..820faaba7efa9a649991e60e53f2ee8e39b1ffe6 100644 (file)
--- a/hwacha/hwacha.cc
+++ b/hwacha/hwacha.cc
@@ -20,9 +20,7 @@ void ct_state_t::reset()
 
 void ut_state_t::reset()
 {
-  run = false;
-  XPR.reset();
-  FPR.reset();
+  memset(this, 0, sizeof(*this));
 }
 
 void hwacha_t::reset()
@@ -76,7 +74,7 @@ static reg_t custom(processor_t* p, insn_t insn, reg_t pc)
   }
 
   if (!matched)
-    h->take_exception(HWACHA_CAUSE_ILLEGAL_INSTRUCTION, insn.bits());
+    h->take_exception(HWACHA_CAUSE_ILLEGAL_INSTRUCTION, uint32_t(insn.bits()));
 
   return npc;
 }
@@ -105,7 +103,5 @@ void hwacha_t::take_exception(reg_t c, reg_t a)
   cause = c;
   aux = a;
   raise_interrupt();
-  if (!(p->get_state()->sr & SR_EI))
-    throw std::logic_error("hwacha exception posted, but SR_EI bit not set!");
-  throw std::logic_error("hwacha exception posted, but IM[COP] bit not set!");
+  throw std::logic_error("unreachable!");
 }