Factor out the dummy RoCC accelerator

[riscv-isa-sim.git] / hwacha / hwacha.mk.in

diff --git a/hwacha/hwacha.mk.in b/hwacha/hwacha.mk.in
index bcda2abcb7957c495309ca1ff35fe58ba30b8cec..362487977838fc976cfe541bef42796d247d5afd 100644 (file)
--- a/hwacha/hwacha.mk.in
+++ b/hwacha/hwacha.mk.in
@@ -1,7 +1,5 @@
-get_insn_list = $(shell sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/' $(1))
-get_opcode = $(shell grep \\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
-
 hwacha_subproject_deps = \
+       spike \
        riscv \
        softfloat \
 
@@ -12,17 +10,21 @@ hwacha_hdrs = \
        hwacha_xcpt.h \
        decode_hwacha.h \
        decode_hwacha_ut.h \
-       decode_hwacha_ut_half.h \
        opcodes_hwacha.h \
        opcodes_hwacha_ut.h \
-       opcodes_hwacha_ut_half.h \
+       insn_template_hwacha.h \
+       insn_template_hwacha_ut.h \
+
+hwacha_precompiled_hdrs = \
+       insn_template_hwacha.h \
+       insn_template_hwacha_ut.h \
 
 hwacha_srcs = \
        hwacha.cc \
        hwacha_disasm.cc \
+       cvt16.cc \
        $(hwacha_gen_srcs) \
        $(hwacha_ut_gen_srcs) \
-       $(hwacha_ut_half_gen_srcs) \
 
 hwacha_test_srcs =
 
@@ -38,8 +40,3 @@ hwacha_ut_gen_srcs = \
 $(hwacha_ut_gen_srcs): %.cc: insns_ut/%.h insn_template_hwacha_ut.cc
        sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/hwacha/insn_template_hwacha_ut.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/hwacha/opcodes_hwacha_ut.h,$(subst .cc,,$@))/' > $@
 
-hwacha_ut_half_gen_srcs = \
-       $(addsuffix .cc, $(call get_insn_list,$(src_dir)/hwacha/opcodes_hwacha_ut_half.h))
-
-$(hwacha_ut_half_gen_srcs): %.cc: insns_ut_half/%.h insn_template_hwacha_ut_half.cc
-       sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/hwacha/insn_template_hwacha_ut_half.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/hwacha/opcodes_hwacha_ut_half.h,$(subst .cc,,$@))/' > $@