Factor out the dummy RoCC accelerator

[riscv-isa-sim.git] / hwacha / hwacha.mk.in

diff --git a/hwacha/hwacha.mk.in b/hwacha/hwacha.mk.in
index bf16b6fba823d4c7bdc2cf82533023dec121379f..362487977838fc976cfe541bef42796d247d5afd 100644 (file)
--- a/hwacha/hwacha.mk.in
+++ b/hwacha/hwacha.mk.in
@@ -1,7 +1,5 @@
-get_insn_list = $(shell cat $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
-get_opcode = $(shell grep \\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
-
 hwacha_subproject_deps = \
+       spike \
        riscv \
        softfloat \
 
@@ -14,10 +12,17 @@ hwacha_hdrs = \
        decode_hwacha_ut.h \
        opcodes_hwacha.h \
        opcodes_hwacha_ut.h \
+       insn_template_hwacha.h \
+       insn_template_hwacha_ut.h \
+
+hwacha_precompiled_hdrs = \
+       insn_template_hwacha.h \
+       insn_template_hwacha_ut.h \
 
 hwacha_srcs = \
        hwacha.cc \
        hwacha_disasm.cc \
+       cvt16.cc \
        $(hwacha_gen_srcs) \
        $(hwacha_ut_gen_srcs) \