Implement "half-baked" half-precision instruction subset for Hwacha

[riscv-isa-sim.git] / hwacha / insns_ut_half / ut_flh.h

diff --git a/hwacha/insns_ut_half/ut_flh.h b/hwacha/insns_ut_half/ut_flh.h
new file mode 100644 (file)
index 0000000..90872ed
--- /dev/null
+++ b/hwacha/insns_ut_half/ut_flh.h
@@ -0,0 +1,2 @@
+require_fp;
+WRITE_FRD(MMU.load_int16(RS1 + insn.i_imm()));