Add vsetprec instruction prototype

[riscv-isa-sim.git] / hwacha / opcodes_hwacha.h

diff --git a/hwacha/opcodes_hwacha.h b/hwacha/opcodes_hwacha.h
index e384b375e79ea9c3a8866467ad9a07e5f1348878..297b3afca604d91a973de66a0e36553168012f1d 100644 (file)
--- a/hwacha/opcodes_hwacha.h
+++ b/hwacha/opcodes_hwacha.h
@@ -26,6 +26,7 @@ DECLARE_INSN(vlsegwu, 0xc00205b, 0x1ff0707f)
 DECLARE_INSN(vmsv, 0x200202b, 0xfff0707f)
 DECLARE_INSN(vmvv, 0x200002b, 0xfff0707f)
 DECLARE_INSN(vsetcfg, 0x200b, 0x7fff)
+DECLARE_INSN(vsetprec, 0x805b, 0xfffff)
 DECLARE_INSN(vsetvl, 0x600b, 0xfff0707f)
 DECLARE_INSN(vssegb, 0x207b, 0x1ff0707f)
 DECLARE_INSN(vssegd, 0x600207b, 0x1ff0707f)