+// See LICENSE for license details.
+
#ifndef __TEST_MACROS_SCALAR_H
#define __TEST_MACROS_SCALAR_H
test_ ## testnum: \
li TESTNUM, testnum; \
li x4, 0; \
-1: la x1, result; \
+1: li x1, result; \
TEST_INSERT_NOPS_ ## src1_nops \
la x2, base; \
TEST_INSERT_NOPS_ ## src2_nops \
li x4, 0; \
1: la x2, base; \
TEST_INSERT_NOPS_ ## src1_nops \
- la x1, result; \
+ li x1, result; \
TEST_INSERT_NOPS_ ## src2_nops \
store_inst x1, offset(x2); \
load_inst x3, offset(x2); \
li x5, 2; \
bne x4, x5, 1b \
-#-----------------------------------------------------------------------
-# Test branch instructions
-#-----------------------------------------------------------------------
-
-#define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \
-test_ ## testnum: \
- li TESTNUM, testnum; \
- li x1, val1; \
- inst x1, 2f; \
- bne x0, TESTNUM, fail; \
-1: bne x0, TESTNUM, 3f; \
-2: inst x1, 1b; \
- bne x0, TESTNUM, fail; \
-3:
-
-#define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \
-test_ ## testnum: \
- li TESTNUM, testnum; \
- li x1, val1; \
- inst x1, 1f; \
- bne x0, TESTNUM, 2f; \
-1: bne x0, TESTNUM, fail; \
-2: inst x1, 1b; \
-3:
-
-#define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \
-test_ ## testnum: \
- li TESTNUM, testnum; \
- li x4, 0; \
-1: li x1, val1; \
- TEST_INSERT_NOPS_ ## nop_cycles \
- inst x1, fail; \
- addi x4, x4, 1; \
- li x5, 2; \
- bne x4, x5, 1b \
-
#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \
test_ ## testnum: \
li TESTNUM, testnum; \
TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3)
-#define TEST_FP_OP1_S( testnum, inst, result, val1 ) \
- TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \
+#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \
inst f3, f0; fmv.x.s a0, f3)
-#define TEST_FP_OP1_D( testnum, inst, result, val1 ) \
- TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \
+#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \
+ inst f3, f0; fmv.x.d a0, f3)
+
+#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
+ inst f3, f0; fmv.x.s a0, f3)
+
+#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \
+ TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \
inst f3, f0; fmv.x.d a0, f3)
#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_D_INTERNAL( testnum, 0, dword result, val1, val2, 0.0, \
inst a0, f0, f1)
+#define TEST_FCLASS_S(testnum, correct, input) \
+ TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \
+ fclass.s a0, fa0)
+
+#define TEST_FCLASS_D(testnum, correct, input) \
+ TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \
+ fclass.d a0, fa0)
+
#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
test_ ## testnum: \
li TESTNUM, testnum; \
.double result; \
1:
-
-#-----------------------------------------------------------------------
-# RV64SV MACROS
-#-----------------------------------------------------------------------
-
-#define TEST_ILLEGAL_TVEC_REGID( testnum, nxreg, nfreg, inst, reg1, reg2) \
- csrs status, SR_EI; \
- la a0, handler ## testnum; \
- csrw evec, a0; \
- vsetcfg nxreg, nfreg; \
- li a0, 4; \
- vsetvl a0, a0; \
- la a0, src1; \
- la a1, src2; \
- vld vx2, a0; \
- vld vx3, a1; \
- lui a0,%hi(vtcode1 ## testnum); \
- vf %lo(vtcode1 ## testnum)(a0); \
- la reg2, dest; \
-illegal ## testnum: \
- inst reg1, reg2; \
- la a3, dest; \
- vsd vx2, a3; \
- fence; \
-vtcode1 ## testnum: \
- add x2, x2, x3; \
- stop; \
-vtcode2 ## testnum: \
- add x2, x2, x3; \
- stop; \
-handler ## testnum: \
- vxcptkill; \
- li TESTNUM,2; \
- vxcptcause a0; \
- li a1,HWACHA_CAUSE_TVEC_ILLEGAL_REGID; \
- bne a0,a1,fail; \
- vxcptaux a0; \
- la a1, illegal ## testnum; \
- lw a2, 0(a1); \
- bne a0, a2, fail; \
- vsetcfg 32,0; \
- li a0,4; \
- vsetvl a0,a0; \
- la a0,src1; \
- la a1,src2; \
- vld vx2,a0; \
- vld vx3,a1; \
- lui a0,%hi(vtcode2 ## testnum); \
- vf %lo(vtcode2 ## testnum)(a0); \
- la a3,dest; \
- vsd vx2,a3; \
- fence; \
- ld a1,0(a3); \
- li a2,5; \
- li TESTNUM,2; \
- bne a1,a2,fail; \
- ld a1,8(a3); \
- li TESTNUM,3; \
- bne a1,a2,fail; \
- ld a1,16(a3); \
- li TESTNUM,4; \
- bne a1,a2,fail; \
- ld a1,24(a3); \
- li TESTNUM,5; \
- bne a1,a2,fail; \
-
-#define TEST_ILLEGAL_VT_REGID( testnum, nxreg, nfreg, inst, reg1, reg2, reg3) \
- csrs status, SR_EI; \
- la a0, handler ## testnum; \
- csrw evec, a0; \
- vsetcfg nxreg, nfreg; \
- li a0, 4; \
- vsetvl a0, a0; \
- la a0, src1; \
- la a1, src2; \
- vld vx2, a0; \
- vld vx3, a1; \
- lui a0,%hi(vtcode1 ## testnum); \
- vf %lo(vtcode1 ## testnum)(a0); \
- la a3, dest; \
- vsd vx2, a3; \
- fence; \
-vtcode1 ## testnum: \
- add x2, x2, x3; \
-illegal ## testnum: \
- inst reg1, reg2, reg3; \
- stop; \
-vtcode2 ## testnum: \
- add x2, x2, x3; \
- stop; \
-handler ## testnum: \
- vxcptkill; \
- li TESTNUM,2; \
- vxcptcause a0; \
- li a1,HWACHA_CAUSE_VF_ILLEGAL_REGID; \
- bne a0,a1,fail; \
- vxcptaux a0; \
- la a1,illegal ## testnum; \
- bne a0,a1,fail; \
- vsetcfg 32,0; \
- li a0,4; \
- vsetvl a0,a0; \
- la a0,src1; \
- la a1,src2; \
- vld vx2,a0; \
- vld vx3,a1; \
- lui a0,%hi(vtcode2 ## testnum); \
- vf %lo(vtcode2 ## testnum)(a0); \
- la a3,dest; \
- vsd vx2,a3; \
- fence; \
- ld a1,0(a3); \
- li a2,5; \
- li TESTNUM,2; \
- bne a1,a2,fail; \
- ld a1,8(a3); \
- li TESTNUM,3; \
- bne a1,a2,fail; \
- ld a1,16(a3); \
- li TESTNUM,4; \
- bne a1,a2,fail; \
- ld a1,24(a3); \
- li TESTNUM,5; \
- bne a1,a2,fail; \
-
#-----------------------------------------------------------------------
# Pass and fail code (assumes test num is in TESTNUM)
#-----------------------------------------------------------------------
#define TEST_PASSFAIL \
bne x0, TESTNUM, pass; \
fail: \
- RVTEST_FAIL \
+ RVTEST_FAIL; \
pass: \
RVTEST_PASS \