-#define SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
- (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<14) | (packed<<15))
+#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1))
-#define SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
- (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (active<<14))
+#define SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \
+ (reg0 | (reg1<<8) | (reg2<<8) | \
+ (shape0<<24) | (shape0<<26) | (shape0<<28))
-#define SET_SV_CSR( type, regkey, elwidth, regidx, isvec, packed ) \
- li x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec, packed ); \
+#define SV_SHAPE_PERM_XYZ 0
+#define SV_SHAPE_PERM_XZY 1
+#define SV_SHAPE_PERM_YXZ 2
+#define SV_SHAPE_PERM_YZX 3
+#define SV_SHAPE_PERM_ZXY 4
+#define SV_SHAPE_PERM_ZYX 5
+
+#define SV_SHAPE_CSR(xd, yd, zd, offs, perm) \
+ ((xd-1) | ((yd-1)<<8) | ((zd-1)<<16) | (perm<<24) | \
+ ((offs&0x1)<<7) | ((offs&0x2)<<14) | ((offs&0x4)<<21) )
+
+
+#define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \
+ (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15))
+#define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \
+ (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15))
+
+#define SET_SV_REMAP_CSR(reg0, shape0, reg1, shape1, reg2, shape2) \
+ li x1, SV_REMAP_CSR( reg0, shape0, reg1, shape1, reg2, shape2); \
+ csrrw x0, 0x4f7, x1
+
+#define SET_SV_SHAPE0_CSR(xd, yd, zd, offs, permute) \
+ li x1, SV_SHAPE_CSR( xd, yd, zd, offs, permute); \
+ csrrw x0, 0x4f8, x1
+
+// series of macros that set one, two or three register (or predicate)
+// key-value table entries that alter the behaviour of the registers
+#define SET_SV_CSR( type, regkey, elwidth, regidx, isvec) \
+ li x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
csrrw x0, 0x4c0, x1
-#define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, active ) \
- li x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, active ); \
+#define SET_SV_CSR2( type, regkey, elwidth, regidx, isvec) \
+ li x1, SV_REG_CSR( type, regkey, elwidth, regidx, isvec); \
+ csrrw x0, 0x4c1, x1
+
+#define SET_SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ) \
+ li x1, SV_PRED_CSR( type, regkey, zero, inv, regidx, packed ); \
csrrw x0, 0x4c8, x1
#define SET_SV_2CSRS( c1, c2 ) \
- li x1, c1 | ((c2)<<16); \
+ li x1, c1 | ((c2)<<16U); \
+ csrrw x0, 0x4c0, x1
+
+#define SET_SV_3CSRS( c1, c2 , c3 ) \
+ li x1, c1 | ((c2)<<16U) | ((c3)<<32U); \
csrrw x0, 0x4c0, x1
#define SET_SV_2PREDCSRS( c1, c2 ) \
- li x1, c1 | ((c2)<<16); \
+ li x1, c1 | ((c2)<<16U); \
csrrw x0, 0x4c8, x1
-#define CLR_SV_CSRS( ) csrrw x0, 0x4c0, 0
+// clears the 2 CSRs set above
+#define CLR_SV_CSRS( ) csrrwi x0, 0x4c0, 0xf;
#define CLR_SV_PRED_CSRS( ) csrrw x0, 0x4c8, 0
-#define SET_SV_MVL( val ) csrrwi x0, 0x4f2, val
-#define SET_SV_VL( val ) csrrwi x0, 0x4f0, val
+// set maximum vector length.
+#define SET_SV_MVL( val ) csrrwi x0, 0x4f1, (val-1)
+
+// set actual vector length: normally that would
+// be vl = xN = min(mvl, min(vl, xN) however we
+// pass in x0 here.
+#define SET_SV_VL( val ) csrrwi x0, 0x4f0, (val-1)
#define SV_LD_DATA( reg, from, offs ) \
la x1, from; \
lw reg, offs(x1)
+#define SV_LDD_DATA( reg, from, offs ) \
+ la x1, from; \
+ ld reg, offs(x1)
+
#define SV_FLD_DATA( reg, from, offs ) \
la x1, from; \
fld reg, offs(x1)
+#define SV_FLW_DATA( reg, from, offs ) \
+ la x1, from; \
+ flw reg, offs(x1)
+
+#define TEST_SV_IMMW( reg, imm ) \
+ li t6, MASK_XLEN(imm) ; \
+ bne reg, t6, fail;
+
#define TEST_SV_IMM( reg, imm ) \
- li x1, imm; \
- bne reg, x1, fail
+ li t6, ((imm) & 0xffffffffffffffff); \
+ bne reg, t6, fail;
#define TEST_SV_FD( flags, freg, from, offs ) \
fsflags x2, x0; \
la x1, from; \
ld x1, offs(x1); \
fmv.x.d x2, freg; \
- bne x2, x1, fail
+ bne x2, x1, fail;
+
+#define TEST_SV_FW( flags, freg, from, offs ) \
+ fsflags x2, x0; \
+ li x1, flags; \
+ bne x2, x1, fail; \
+ la x1, from; \
+ lw x1, offs(x1); \
+ fmv.x.s x2, freg; \
+ bne x2, x1, fail;
+
+#define SV_LOAD_FORMAT_NO_OFFSET(load_instruction, testdata, elwidth) \
+ load_instruction( x12, testdata); \
+ load_instruction( x13, testdata+elwidth); \
+ load_instruction( x14, testdata+elwidth*2); \
+ load_instruction( x15, testdata+elwidth*3); \
+ load_instruction( x16, testdata+elwidth*4); \
+ load_instruction( x17, testdata++elwidth*5); \
+
+#define SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth) \
+ load_instruction( x12, testdata, 0); \
+ load_instruction( x13, testdata+elwidth, 0); \
+ load_instruction( x14, testdata+elwidth*2, 0); \
+ load_instruction( x15, testdata+elwidth*3, 0); \
+ load_instruction( x16, testdata+elwidth*4, 0); \
+ load_instruction( x17, testdata+elwidth*5, 0); \
+
+#define SV_ELWIDTH_TEST(code, load_instruction, testdata, elwidth, \
+ vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3 ) \
+ \
+ SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT_OFFSET(load_instruction, testdata, elwidth), \
+ vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3, code x28, x15, x12) \
+
+#define SV_ELWIDTH_TEST_LOAD(code, load_instruction, testdata, elwidth, \
+ vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3 ) \
+ \
+ SV_ELWIDTH_TEST_INNER(SV_LOAD_FORMAT_NO_OFFSET(load_instruction, testdata, elwidth), \
+ vl, wid1, wid2, wid3, isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3, code x28, x15, x12) \
+
+#define SV_ELWIDTH_TEST_INNER(load_type, vl, wid1, wid2, wid3, \
+ isvec1, isvec2, isvec3, \
+ expect1, expect2, expect3, code... ) \
+ load_type; \
+ \
+ li x28, 0xa5a5a5a5a5a5a5a5; \
+ li x29, 0xa5a5a5a5a5a5a5a5; \
+ li x30, 0xa5a5a5a5a5a5a5a5; \
+ \
+ SET_SV_MVL( vl ); \
+ SET_SV_3CSRS( SV_REG_CSR( 1, 15, wid1, 15, isvec1), \
+ SV_REG_CSR( 1, 12, wid2, 12, isvec2), \
+ SV_REG_CSR( 1, 28, wid3, 28, isvec3)); \
+ SET_SV_VL( vl ); \
+ \
+ code; \
+ \
+ CLR_SV_CSRS(); \
+ SET_SV_VL( 1); \
+ SET_SV_MVL( 1); \
+ \
+ TEST_SV_IMM( x28, expect1 ); \
+ TEST_SV_IMM( x29, expect2 ); \
+ TEST_SV_IMM( x30, expect3 ); \
+
+#define SV_W_DFLT 0
+#define SV_W_8BIT 1
+#define SV_W_16BIT 2
+#define SV_W_32BIT 3