#ifndef __TEST_MACROS_VECTOR_H
#define __TEST_MACROS_VECTOR_H
+#undef EXTRA_INIT
+#define EXTRA_INIT RVTEST_VEC_ENABLE
#-----------------------------------------------------------------------
# Helper macros
#define TEST_CASE_NREG( testnum, nxreg, nfreg, testreg, correctval, code... ) \
test_ ## testnum: \
+ vsetcfg nxreg,nfreg; \
li a3,2048; \
- vvcfgivl a3,a3,nxreg,nfreg; \
+ vsetvl a3,a3; \
lui a0,%hi(vtcode ## testnum ); \
vf %lo(vtcode ## testnum )(a0); \
la a4,dst; \
vsd v ## testreg, a4; \
- fence.v.l; \
+ fence; \
li a1,correctval; \
li a2,0; \
- li x28, testnum; \
+ li TESTNUM, testnum; \
test_loop ## testnum: \
ld a0,0(a4); \
beq a0,a1,skip ## testnum; \
# Tests for instructions with immediate operand
#-----------------------------------------------------------------------
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
TEST_CASE_NREG( testnum, 4, 0, x3, result, \
li x1, val1; \
- inst x3, x1, imm; \
+ inst x3, x1, SEXT_IMM(imm); \
)
#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
TEST_CASE_NREG( testnum, 2, 0, x1, result, \
li x1, val1; \
- inst x1, x1, imm; \
+ inst x1, x1, SEXT_IMM(imm); \
)
#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
TEST_CASE_NREG( testnum, 5, 0, x4, result, \
li x1, val1; \
- inst x3, x1, imm; \
+ inst x3, x1, SEXT_IMM(imm); \
TEST_INSERT_NOPS_ ## nop_cycles \
addi x4, x3, 0; \
)
TEST_CASE_NREG( testnum, 4, 0, x3, result, \
li x1, val1; \
TEST_INSERT_NOPS_ ## nop_cycles \
- inst x3, x1, imm; \
+ inst x3, x1, SEXT_IMM(imm); \
)
#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
TEST_CASE_NREG( testnum, 2, 0, x1, result, \
- inst x1, x0, imm; \
+ inst x1, x0, SEXT_IMM(imm); \
)
#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
TEST_CASE_NREG( testnum, 2, 0, x0, 0, \
li x1, val1; \
- inst x0, x1, imm; \
+ inst x0, x1, SEXT_IMM(imm); \
)
#-----------------------------------------------------------------------
#define TEST_FP_OP_S_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
test_ ## testnum: \
+ vsetcfg nxreg,nfreg; \
li a3,2048; \
- vvcfgivl a3,a3,nxreg,nfreg; \
+ vsetvl a3,a3; \
la a5, test_ ## testnum ## _data ;\
vflstw vf0, a5, x0; \
addi a5,a5,4; \
vf %lo(vtcode ## testnum )(a0); \
la a4,dst; \
vsw vx1, a4; \
- fence.v.l; \
+ fence; \
lw a1, 0(a5); \
li a2, 0; \
- li x28, testnum; \
+ li TESTNUM, testnum; \
test_loop ## testnum: \
lw a0,0(a4); \
beq a0,a1,skip ## testnum; \
addi a4,a4,4; \
addi a2,a2,1; \
bne a2,a3,test_loop ## testnum; \
- b 1f; \
+ j 1f; \
vtcode ## testnum : \
code; \
stop; \
#define TEST_FP_OP_D_INTERNAL_NREG( testnum, nxreg, nfreg, result, val1, val2, val3, code... ) \
test_ ## testnum: \
+ vsetcfg nxreg,nfreg; \
li a3,2048; \
- vvcfgivl a3,a3,nxreg,nfreg; \
+ vsetvl a3,a3; \
la a5, test_ ## testnum ## _data ;\
vflstd vf0, a5, x0; \
addi a5,a5,8; \
vf %lo(vtcode ## testnum )(a0); \
la a4,dst; \
vsd vx1, a4; \
- fence.v.l; \
+ fence; \
ld a1, 0(a5); \
li a2, 0; \
- li x28, testnum; \
+ li TESTNUM, testnum; \
test_loop ## testnum: \
ld a0,0(a4); \
beq a0,a1,skip ## testnum; \
addi a4,a4,8; \
addi a2,a2,1; \
bne a2,a3,test_loop ## testnum; \
- b 1f; \
+ j 1f; \
vtcode ## testnum : \
code; \
stop; \
TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, 0.0, 0.0, \
fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s x1, f3)
-#define TEST_FP_OP2_S( testnum, inst, result, val1, val2 ) \
+#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, 0.0, \
inst f3, f0, f1; fmv.x.s x1, f3)
-#define TEST_FP_OP2_D( testnum, inst, result, val1, val2 ) \
+#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \
TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, 0.0, \
inst f3, f0, f1; fmv.x.d x1, f3)
-#define TEST_FP_OP3_S( testnum, inst, result, val1, val2, val3 ) \
+#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \
TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, float result, val1, val2, val3, \
inst f3, f0, f1, f2; fmv.x.s x1, f3)
-#define TEST_FP_OP3_D( testnum, inst, result, val1, val2, val3 ) \
+#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \
TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, double result, val1, val2, val3, \
inst f3, f0, f1, f2; fmv.x.d x1, f3)
-#define TEST_FP_INT_OP_S( testnum, inst, result, val1, rm ) \
+#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \
TEST_FP_OP_S_INTERNAL_NREG( testnum, 2, 4, word result, val1, 0.0, 0.0, \
inst x1, f0, rm)
-#define TEST_FP_INT_OP_D( testnum, inst, result, val1, rm ) \
+#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \
TEST_FP_OP_D_INTERNAL_NREG( testnum, 2, 4, dword result, val1, 0.0, 0.0, \
inst x1, f0, rm)
#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \
test_ ## testnum: \
+ vsetcfg 2,1; \
li a3,2048; \
- vvcfgivl a3,a3,2,1; \
+ vsetvl a3,a3; \
lui a0,%hi(vtcode ## testnum ); \
vf %lo(vtcode ## testnum )(a0); \
la a4,dst; \
vsw vx1, a4; \
- fence.v.l; \
+ fence; \
la a5, test_ ## testnum ## _data ;\
lw a1, 0(a5); \
li a2, 0; \
- li x28, testnum; \
+ li TESTNUM, testnum; \
test_loop ## testnum: \
lw a0,0(a4); \
beq a0,a1,skip ## testnum; \
addi a4,a4,4; \
addi a2,a2,1; \
bne a2,a3,test_loop ## testnum; \
- b 1f; \
+ j 1f; \
vtcode ## testnum : \
li x1, val1; \
inst f0, x1; \
#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \
test_ ## testnum: \
+ vsetcfg 2,1; \
li a3,2048; \
- vvcfgivl a3,a3,2,1; \
+ vsetvl a3,a3; \
lui a0,%hi(vtcode ## testnum ); \
vf %lo(vtcode ## testnum )(a0); \
la a4,dst; \
vsd vx1, a4; \
- fence.v.l; \
+ fence; \
la a5, test_ ## testnum ## _data ;\
ld a1, 0(a5); \
li a2, 0; \
- li x28, testnum; \
+ li TESTNUM, testnum; \
test_loop ## testnum: \
ld a0,0(a4); \
beq a0,a1,skip ## testnum; \
addi a4,a4,8; \
addi a2,a2,1; \
bne a2,a3,test_loop ## testnum; \
- b 1f; \
+ j 1f; \
vtcode ## testnum : \
li x1, val1; \
inst f0, x1; \
#define TEST_CASE_NREG_MEM( testnum, nxreg, nfreg, correctval, code... ) \
test_ ## testnum: \
+ vsetcfg nxreg,nfreg; \
li a3,2048; \
- vvcfgivl a3,a3,nxreg,nfreg; \
+ vsetvl a3,a3; \
lui a0,%hi(vtcode ## testnum ); \
vf %lo(vtcode ## testnum )(a0); \
la a4,dst; \
- fence.v.l; \
+ fence; \
li a1,correctval; \
li a2,0; \
- li x28, testnum; \
+ li TESTNUM, testnum; \
test_loop ## testnum: \
ld a0,0(a4); \
beq a0,a1,skip ## testnum; \
)
#-----------------------------------------------------------------------
-# Pass and fail code (assumes test num is in x28)
+# Pass and fail code (assumes test num is in TESTNUM)
#-----------------------------------------------------------------------
#define TEST_PASSFAIL \
- bne x0, x28, pass; \
+ bne x0, TESTNUM, pass; \
fail: \
RVTEST_FAIL \
pass: \