Update to new privileged ISA

[riscv-tests.git] / isa / macros / vector / test_macros.h

diff --git a/isa/macros/vector/test_macros.h b/isa/macros/vector/test_macros.h
index 59e9e77bcb1a250fa66cc8ce401cb827d328c372..932aba3c4affeeaa95eb8c6dc1aac44148906b18 100644 (file)
--- a/isa/macros/vector/test_macros.h
+++ b/isa/macros/vector/test_macros.h
@@ -64,22 +64,24 @@ next ## testnum :
 # Tests for instructions with immediate operand
 #-----------------------------------------------------------------------
 
+#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11))
+
 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
       li  x1, val1; \
-      inst x3, x1, imm; \
+      inst x3, x1, SEXT_IMM(imm); \
     )
 
 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
       li  x1, val1; \
-      inst x1, x1, imm; \
+      inst x1, x1, SEXT_IMM(imm); \
     )
 
 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
     TEST_CASE_NREG( testnum, 5, 0, x4, result, \
       li  x1, val1; \
-      inst x3, x1, imm; \
+      inst x3, x1, SEXT_IMM(imm); \
       TEST_INSERT_NOPS_ ## nop_cycles \
       addi  x4, x3, 0; \
     )
@@ -88,18 +90,18 @@ next ## testnum :
     TEST_CASE_NREG( testnum, 4, 0, x3, result, \
       li  x1, val1; \
       TEST_INSERT_NOPS_ ## nop_cycles \
-      inst x3, x1, imm; \
+      inst x3, x1, SEXT_IMM(imm); \
     )
 
 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
     TEST_CASE_NREG( testnum, 2, 0, x1, result, \
-      inst x1, x0, imm; \
+      inst x1, x0, SEXT_IMM(imm); \
     )
 
 #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \
     TEST_CASE_NREG( testnum, 2, 0, x0, 0, \
       li  x1, val1; \
-      inst x0, x1, imm; \
+      inst x0, x1, SEXT_IMM(imm); \
     )
 
 #-----------------------------------------------------------------------