Clear triggers during entry.

[riscv-tests.git] / isa / rv32si / Makefrag

diff --git a/isa/rv32si/Makefrag b/isa/rv32si/Makefrag
index e03819f9f964e963c7b0a67eb10cd7c07564d1b7..f4237883d20e3d183e9db34c7c7d5a9e948f8e4f 100644 (file)
--- a/isa/rv32si/Makefrag
+++ b/isa/rv32si/Makefrag
@@ -4,12 +4,12 @@
 
 rv32si_sc_tests = \
        csr \
-       shamt \
+       dirty \
        ma_fetch \
-       illegal \
        scall \
        sbreak \
-       ma_addr \
-       timer \
+       wfi \
 
 rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests))
+
+spike32_tests += $(rv32si_p_tests)