Make JALR test sensible in RISC-V, rather than SMIPS

[riscv-tests.git] / isa / rv32ui / sh.S

diff --git a/isa/rv32ui/sh.S b/isa/rv32ui/sh.S
index 1da7a832c397ccade0b9de242d07501a511d54c2..387e18126c4bc8e089ec95391d5a9a1a33758424 100644 (file)
--- a/isa/rv32ui/sh.S
+++ b/isa/rv32ui/sh.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # sh.S
 #-----------------------------------------------------------------------------
@@ -17,13 +19,7 @@ RVTEST_CODE_BEGIN
 
   TEST_ST_OP( 2, lh, sh, 0x000000aa, 0, tdat );
   TEST_ST_OP( 3, lh, sh, 0xffffaa00, 2, tdat );
-#ifdef __RISCVEL
   TEST_ST_OP( 4, lw, sh, 0xbeef0aa0, 4, tdat );
-#elif defined(__RISCVEB)
-#else
-  TEST_ST_OP( 4, lw, sh, 0x0aa0beef, 4, tdat );
-#error unknown endianness!
-#endif
   TEST_ST_OP( 5, lh, sh, 0xffffa00a, 6, tdat );
 
   # Test with negative offset