Add missing rv32mi/rv32si tests

[riscv-tests.git] / isa / rv64mi / mcsr.S

diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
index 8a451ca6bf91bb00104359041e8d7acabb02d338..2eeb14cdb6247f977ee2d79a8606fbbb09e2b6ac 100644 (file)
--- a/isa/rv64mi/mcsr.S
+++ b/isa/rv64mi/mcsr.S
@@ -13,8 +13,12 @@
 RVTEST_RV64M
 RVTEST_CODE_BEGIN
 
-  # Check that mcpuid reports RV64
+  # Check that mcpuid reports the correct XLEN
+#ifdef __riscv64
   TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62)
+#else
+  TEST_CASE(2, a0, 0x0, csrr a0, misa; srl a0, a0, 30)
+#endif
 
   # Check that mhartid reports 0
   TEST_CASE(3, a0, 0x0, csrr a0, mhartid)