Update to new breakpoint & counter spec

[riscv-tests.git] / isa / rv64si / csr.S

diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 26031bc7e58f1cf3ac0154276803b9446a731ac2..1f7bb7722a7b1a840c36118a03795bf23eac943e 100644 (file)
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # csr.S
 #-----------------------------------------------------------------------------
@@ -11,18 +13,89 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  csrwi sup0, 3
-  TEST_CASE( 2, a0,         3, csrr a0, sup0);
-  TEST_CASE( 3, a1,         3, csrrci a1, sup0, 1);
-  TEST_CASE( 4, a2,         2, csrrsi a2, sup0, 4);
-  TEST_CASE( 5, a3,         6, csrrwi a3, sup0, 2);
-  TEST_CASE( 6, a1,         2, li a0, 0xbad1dea; csrrw a1, sup0, a0);
-  TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sup0, a0);
-  TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sup0, a0);
-  TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sup0);
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define sret mret
+  #define stvec_handler mtvec_handler
+  #undef SSTATUS_SPP
+  #define SSTATUS_SPP MSTATUS_MPP
+#endif
+
+  csrwi sscratch, 3
+  TEST_CASE( 2, a0,         3, csrr a0, sscratch);
+  TEST_CASE( 3, a1,         3, csrrci a1, sscratch, 1);
+  TEST_CASE( 4, a2,         2, csrrsi a2, sscratch, 4);
+  TEST_CASE( 5, a3,         6, csrrwi a3, sscratch, 2);
+  TEST_CASE( 6, a1,         2, li a0, 0xbad1dea; csrrw a1, sscratch, a0);
+  TEST_CASE( 7, a0, 0xbad1dea, li a0, 0x0001dea; csrrc a0, sscratch, a0);
+  TEST_CASE( 8, a0, 0xbad0000, li a0, 0x000beef; csrrs a0, sscratch, a0);
+  TEST_CASE( 9, a0, 0xbadbeef, csrr a0, sscratch);
+
+#ifdef __MACHINE_MODE
+  # Figure out if 'U' is set in misa
+  csrr a0, misa   # a0 = csr(misa)
+  srli a0, a0, 20 # a0 = a0 >> 20
+  andi a0, a0, 1  # a0 = a0 & 1
+  beqz a0, finish # if no user mode, skip the rest of these checks
+#endif
+
+  # jump to user land
+  li t0, SSTATUS_SPP
+  csrc sstatus, t0
+  la t0, 1f
+  csrw sepc, t0
+  sret
+  1:
+
+  # Make sure writing the cycle counter causes an exception.
+  # Don't run in supervisor, as we don't delegate illegal instruction traps.
+#ifdef __MACHINE_MODE
+  TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0);
+#endif
 
+  # Make sure reading status in user mode causes an exception.
+  # Don't run in supervisor, as we don't delegate illegal instruction traps.
+#ifdef __MACHINE_MODE
+  TEST_CASE(11, a0, 255, li a0, 255; csrr a0, sstatus)
+#else
+  TEST_CASE(11, x0, 0, nop)
+#endif
+
+finish:
+  RVTEST_PASS
+
+  # We should only fall through to this if scall failed.
   TEST_PASSFAIL
 
+  .align 2
+stvec_handler:
+  # Trapping on tests 10 and 11 is good news.
+  # Note that since the test didn't complete, TESTNUM is smaller by 1.
+  li t0, 9
+  beq TESTNUM, t0, privileged
+  li t0, 10
+  beq TESTNUM, t0, privileged
+
+  # catch RVTEST_PASS and kick it up to M-mode
+  csrr t0, scause
+  li t1, CAUSE_USER_ECALL
+  bne t0, t1, fail
+  RVTEST_PASS
+
+privileged:
+  # Make sure scause indicates a lack of privilege.
+  csrr t0, scause
+  li t1, CAUSE_ILLEGAL_INSTRUCTION
+  bne t0, t1, fail
+  # Return to user mode, but skip the trapping instruction.
+  csrr t0, sepc
+  addi t0, t0, 4
+  csrw sepc, t0
+  sret
+
 RVTEST_CODE_END
 
   .data