Add timer interrupt test

[riscv-tests.git] / isa / rv64si / ipi.S

diff --git a/isa/rv64si/ipi.S b/isa/rv64si/ipi.S
index 95a108a8f3922f15ceeb9a929642d92be753baba..3b0334879b3debdd8879881b13cb98666c084065 100644 (file)
--- a/isa/rv64si/ipi.S
+++ b/isa/rv64si/ipi.S
@@ -15,10 +15,8 @@ RVTEST_CODE_BEGIN
   la a0, handler
   csrw evec, a0
   csrw clear_ipi, x0
-  csrr a0, status
-  li a1, SR_EI | (1 << (IRQ_IPI + SR_IM_SHIFT))
-  or a0, a0, a1
-  csrw status, a0
+  li a0, SR_EI | (1 << (IRQ_IPI + SR_IM_SHIFT))
+  csrs status, a0
 
   # wait for all cores to boot
   la a0, coreid