Mask off large constants for RV32

[riscv-tests.git] / isa / rv64si / ma_fetch.S

diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index db702d96773c8ba7cc03eddc291cb46dbec99770..7766c696ce6c195c2384c1ffef0c60aaca8b6f13 100644 (file)
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -18,6 +18,7 @@ RVTEST_CODE_BEGIN
   #define sstatus mstatus
   #define scause mcause
   #define sepc mepc
+  #define sret mret
   #define stvec_handler mtvec_handler
 #endif
 
@@ -31,9 +32,10 @@ RVTEST_CODE_BEGIN
   jalr t1, t0, 2
 1:
   .option rvc
-  c.j fail
+  c.j 1f
   c.j 2f
   .option norvc
+1:
   j fail
 2:
 
@@ -52,9 +54,10 @@ RVTEST_CODE_BEGIN
   jalr t1, t0, 3
 1:
   .option rvc
-  c.j fail
+  c.j 1f
   c.j 2f
   .option norvc
+1:
   j fail
 2:
 
@@ -62,6 +65,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+  .align 2
 stvec_handler:
   # tests 2 and 4 should trap
   li a0, 2