Permit flexible dirty-bit behavior

[riscv-tests.git] / isa / rv64si / wfi.S

diff --git a/isa/rv64si/wfi.S b/isa/rv64si/wfi.S
index 6b1e81899e8ea5841bb13345d47c1c18f23d313e..03020342bcb5ad7979be96173dac3b048f0054f9 100644 (file)
--- a/isa/rv64si/wfi.S
+++ b/isa/rv64si/wfi.S
@@ -13,18 +13,10 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-#ifdef __MACHINE_MODE
-  #define sstatus mstatus
-  #define sip mip
-  #undef MIP_SSIP
-  #define MIP_SSIP MIP_MSIP
-  #undef SSTATUS_SIE
-  #define SSTATUS_SIE MSTATUS_MIE
-#endif
-
-  # Make sure wfi doesn't stall if an interrupt is pending, even if masked
+  # Make sure wfi doesn't halt the hart, even if interrupts are disabled
   csrc sstatus, SSTATUS_SIE
-  csrs sip, MIP_SSIP
+  csrs sie, SIP_SSIP
+  csrs sip, SIP_SSIP
   wfi
 
   RVTEST_PASS