correctly set SR_EA bit for all vector physical supervisor tests

[riscv-tests.git] / isa / rv64sv / illegal_cfg_nfpr.S

diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S
index b27126807cd3ef3ced1f5e5121486cb20177073d..2440cbbf745e9a8fa85988cc134c55a828829855 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nfpr.S
+++ b/isa/rv64sv/illegal_cfg_nfpr.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler