split out S-mode tests and M-mode tests

[riscv-tests.git] / isa / rv64sv / illegal_tvec_regid.S

diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S
index 4f48f8f61cd60bf695092f805334f0bdd378c2d3..30403baaf88c175ede1c209221e3eb4ea7885caa 100644 (file)
--- a/isa/rv64sv/illegal_tvec_regid.S
+++ b/isa/rv64sv/illegal_tvec_regid.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # illegal_tvec_regid.S
 #-----------------------------------------------------------------------------
@@ -8,23 +10,21 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  mfpcr a0,cr0
-  li a1,1
-  slli a2,a1,8
-  or a0,a0,a1 # enable traps
-  mtpcr a0,cr0
-
-  TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2, 0x931c7)
-  TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2, 0x831c7)
+  TEST_ILLEGAL_TVEC_REGID(2, 5, 5, vsd, vx7, a2)
+  TEST_ILLEGAL_TVEC_REGID(3, 5, 5, vld, vx7, a2)
 
-  TEST_ILLEGAL_TVEC_REGID(4, 5, 5, vfsd, vf7, a2, 0x9b9e7)
-  TEST_ILLEGAL_TVEC_REGID(5, 5, 5, vfld, vf7, a2, 0x8b9e7)
+  TEST_ILLEGAL_TVEC_REGID(4, 5, 5, vfsd, vf7, a2)
+  TEST_ILLEGAL_TVEC_REGID(5, 5, 5, vfld, vf7, a2)
 
   TEST_PASSFAIL
 
+# the handler gets rewritten for every test, but need this for the framework
+stvec_handler:
+  j fail
+
 RVTEST_CODE_END
 
   .data