correctly set SR_EA bit for all vector physical supervisor tests

[riscv-tests.git] / isa / rv64sv / ma_utsd.S

diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index ead6c2c0ed6a5a717f00fbcdafc43e5c434e510e..20249e3334d60ddeac8d0c70745cdd9150241c4c 100644 (file)
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler