Update to new privileged ISA

[riscv-tests.git] / isa / rv64sv / ma_utsd.S

diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index 3b9e094a77746c88130ab6482484a57a9c610fa6..3879d51faf7708b5d0a6241708502aa927317b97 100644 (file)
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -10,15 +10,17 @@
 
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
-
-  mfpcr a3,cr0
-  li a4,1
-  slli a5,a4,8
-  or a3,a3,a4 # enable traps
-  mtpcr a3,cr0
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,cr3 # set exception handler
+  csrw evec,a3 # set exception handler
+
+  csrr a3,status
+  li a4,(1 << IRQ_COP)
+  slli a4,a4,SR_IM_SHIFT
+  or a3,a3,a4 # enable IM[COP]
+  csrw status,a3
 
   vsetcfg 32,0
   li a3,4
@@ -46,12 +48,12 @@ handler:
   li x28,2
 
   # check cause
-  mfpcr a3,cr6
-  li a4,29
+  vxcptcause a3
+  li a4,HWACHA_CAUSE_MISALIGNED_STORE
   bne a3,a4,fail
 
   # check vec irq aux
-  mfpcr a3,cr2
+  vxcptaux a3
   la a4, dest+1
   bne a3,a4,fail