split out S-mode tests and M-mode tests

[riscv-tests.git] / isa / rv64sv / ma_vld.S

diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index 4276b6495887161623aa97c023147f7ca81c6597..2cdc2d43dcafb1eee5b5eb98ac7f61cfc5d6156e 100644 (file)
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -35,18 +32,18 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_MISALIGNED_LOAD
   bne a3,a4,fail
 
   # check vec irq aux
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,dest+1
   bne a3,a4,fail