correctly set SR_EA bit for all vector physical supervisor tests

[riscv-tests.git] / isa / rv64sv / ma_vld.S

diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index 3ea11e9d1b0e459d8d1d054d950f40efe7ec980f..b353c431bb559727615eef5a3d1ad177e7f50870 100644 (file)
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -11,6 +11,7 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
+  setpcr status, SR_EA # enable accelerator
   setpcr status, SR_EI # enable interrupt
 
   la a3,handler