split out S-mode tests and M-mode tests

[riscv-tests.git] / isa / rv64sv / ma_vt_inst.S

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index 185924ce1cdbfad31a943e778b9a7d4ca660a01d..a2579425e0abf020104a7200d29cc574aca28377 100644 (file)
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # ma_vt_inst.S
 #-----------------------------------------------------------------------------
@@ -8,18 +10,9 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  mfpcr a3,cr0
-  li a4,1
-  slli a5,a4,8
-  or a3,a3,a4 # enable traps
-  mtpcr a3,cr0
-
-  la a3,handler
-  mtpcr a3,cr3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -32,19 +25,21 @@ vtcode1:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
-  li x28,2
+  li TESTNUM,2
 
   # check cause
-  mfpcr a3,cr6
-  li a4,24
+  csrr a3, scause
+  li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
   bne a3,a4,fail
 
   # check badvaddr
-  mfpcr a3,cr2
+  csrr a3, sbadaddr
   la a4,vtcode1+2
+  andi a3, a3, -4 # mask off lower bits so that may
+  andi a4, a4, -4 # ignore impl. specific behavior
   bne a3,a4,fail
 
   # make sure vector unit has cleared out
@@ -64,16 +59,16 @@ handler:
 
   ld a1,0(a5)
   li a2,5
-  li x28,2
+  li TESTNUM,2
   bne a1,a2,fail
   ld a1,8(a5)
-  li x28,3
+  li TESTNUM,3
   bne a1,a2,fail
   ld a1,16(a5)
-  li x28,4
+  li TESTNUM,4
   bne a1,a2,fail
   ld a1,24(a5)
-  li x28,5
+  li TESTNUM,5
   bne a1,a2,fail
 
   TEST_PASSFAIL