split out S-mode tests and M-mode tests

[riscv-tests.git] / isa / rv64sv / ma_vt_inst.S

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index cd7762dc325ca3bcf1dbb2cdaa179c236a8fe384..a2579425e0abf020104a7200d29cc574aca28377 100644 (file)
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # ma_vt_inst.S
 #-----------------------------------------------------------------------------
@@ -8,21 +10,9 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64S
+RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  li a0, SR_EA | SR_EI
-  csrs status, a0
-
-  la a3,handler
-  csrw evec,a3
-
-  csrr a3,status
-  li a4,(1 << IRQ_COP)
-  slli a4,a4,SR_IM_SHIFT
-  or a3,a3,a4 # enable IM[COP]
-  csrw status,a3
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -35,19 +25,21 @@ vtcode1:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
   bne a3,a4,fail
 
   # check badvaddr
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,vtcode1+2
+  andi a3, a3, -4 # mask off lower bits so that may
+  andi a4, a4, -4 # ignore impl. specific behavior
   bne a3,a4,fail
 
   # make sure vector unit has cleared out