Add another FP recoding test case

[riscv-tests.git] / isa / rv64sv / ma_vt_inst.S

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index 25c23c512b49907b377550dacf5540a9397ae7a1..a2579425e0abf020104a7200d29cc574aca28377 100644 (file)
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -28,18 +25,18 @@ vtcode1:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2
 
   # check cause
-  vxcptcause a3
+  csrr a3, scause
   li a4,HWACHA_CAUSE_VF_MISALIGNED_FETCH
   bne a3,a4,fail
 
   # check badvaddr
-  vxcptaux a3
+  csrr a3, sbadaddr
   la a4,vtcode1+2
   andi a3, a3, -4 # mask off lower bits so that may
   andi a4, a4, -4 # ignore impl. specific behavior