Update to new privileged ISA

[riscv-tests.git] / isa / rv64sv / ma_vt_inst.S

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index 85667e42c04314dfc058f54a1c16ad5cb23e3314..c8ef5ad143c1df92fc95b6ea53119d969f8f1139 100644 (file)
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -11,17 +11,17 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  setpcr status, SR_EA # enable accelerator
-  setpcr status, SR_EI # enable interrupt
+  li a0, SR_EA | SR_EI
+  csrs status, a0
 
   la a3,handler
-  mtpcr a3,evec # set exception handler
+  csrw evec,a3
 
-  mfpcr a3,status
+  csrr a3,status
   li a4,(1 << IRQ_COP)
   slli a4,a4,SR_IM_SHIFT
   or a3,a3,a4 # enable IM[COP]
-  mtpcr a3,status
+  csrw status,a3
 
   vsetcfg 32,0
   li a3,4