split up rv64uf and rv64ud isa tests

[riscv-tests.git] / isa / rv64ud / fclass.S

diff --git a/isa/rv64ud/fclass.S b/isa/rv64ud/fclass.S
new file mode 100644 (file)
index 0000000..3daace0
--- /dev/null
+++ b/isa/rv64ud/fclass.S
@@ -0,0 +1,44 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fclass.S
+#-----------------------------------------------------------------------------
+#
+# Test fclass.d instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64UF
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  #define TEST_FCLASS_D(testnum, correct, input) \
+    TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \
+                                    fclass.d a0, fa0)
+
+  TEST_FCLASS_D( 2, 1 << 0, 0xfff0000000000000 )
+  TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 )
+  TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff )
+  TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 )
+  TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 )
+  TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff )
+  TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 )
+  TEST_FCLASS_D( 9, 1 << 7, 0x7ff0000000000000 )
+  TEST_FCLASS_D(10, 1 << 8, 0x7ff0000000000001 )
+  TEST_FCLASS_D(11, 1 << 9, 0x7ff8000000000000 )
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END