Remove instruction width assumptions to support RVC

[riscv-tests.git] / isa / rv64ui / fence_i.S

diff --git a/isa/rv64ui/fence_i.S b/isa/rv64ui/fence_i.S
index 2c51c9cc9f2763c3821a9087f1f97e192c319075..f2076c8f54c2d71d6058c7502b0176f0c05607ec 100644 (file)
--- a/isa/rv64ui/fence_i.S
+++ b/isa/rv64ui/fence_i.S
@@ -22,6 +22,7 @@ lw a0, 0(a0)
 # test I$ hit
 .align 6
 sw a0, 0(a1)
+.align 2
 fence.i
 
 1: addi a3, a3, 222