Add block test.

[riscv-tests.git] / isa / rv64ui / jal.S

diff --git a/isa/rv64ui/jal.S b/isa/rv64ui/jal.S
index 90d06e92b13ed15bd9e20e30597b124e26385cfe..f7f299d210277694f5a9056db6eb1ef770386c53 100644 (file)
--- a/isa/rv64ui/jal.S
+++ b/isa/rv64ui/jal.S
@@ -21,8 +21,8 @@ test_2:
   li  TESTNUM, 2
   li  ra, 0
 
+  jal x3, target_2
 linkaddr_2:
-  jal target_2
   nop
   nop
 
@@ -30,22 +30,21 @@ linkaddr_2:
 
 target_2:
   la  x2, linkaddr_2
-  addi x2, x2, 4
-  bne x2, ra, fail
+  bne x2, x3, fail
 
   #-------------------------------------------------------------
   # Test delay slot instructions not executed nor bypassed
   #-------------------------------------------------------------
 
-  TEST_CASE( 3, x2, 3, \
-    li  x2, 1; \
-    jal 1f; \
-    addi x2, x2, 1; \
-    addi x2, x2, 1; \
-    addi x2, x2, 1; \
-    addi x2, x2, 1; \
-1:  addi x2, x2, 1; \
-    addi x2, x2, 1; \
+  TEST_CASE( 3, ra, 3, \
+    li  ra, 1; \
+    jal x0, 1f; \
+    addi ra, ra, 1; \
+    addi ra, ra, 1; \
+    addi ra, ra, 1; \
+    addi ra, ra, 1; \
+1:  addi ra, ra, 1; \
+    addi ra, ra, 1; \
   )
 
   TEST_PASSFAIL