Make pylint happy.

[riscv-tests.git] / isa / rv64ui / jalr.S

diff --git a/isa/rv64ui/jalr.S b/isa/rv64ui/jalr.S
index 210973ede7b2dd6a6e3f0c95e57819c006ce683e..f27005a5ee2cef96ecfaf4796ad8ac8503db616d 100644 (file)
--- a/isa/rv64ui/jalr.S
+++ b/isa/rv64ui/jalr.S
@@ -42,6 +42,9 @@ target_2:
   # Test delay slot instructions not executed nor bypassed
   #-------------------------------------------------------------
 
+  .option push
+  .align 2
+  .option norvc
   TEST_CASE( 7, t0, 4, \
     li  t0, 1; \
     la  t1, 1f; \
@@ -53,6 +56,7 @@ target_2:
 1:  addi t0, t0, 1; \
     addi t0, t0, 1; \
   )
+  .option pop
 
   TEST_PASSFAIL