Ensure there are no unnamed registers.

[riscv-tests.git] / isa / rv64ui / sb.S

diff --git a/isa/rv64ui/sb.S b/isa/rv64ui/sb.S
index aefeaa0371e9d593814b93237d37dad576fc8189..19e32d640337da9faf55bf3fc320ff19660923f2 100644 (file)
--- a/isa/rv64ui/sb.S
+++ b/isa/rv64ui/sb.S
@@ -19,13 +19,7 @@ RVTEST_CODE_BEGIN
 
   TEST_ST_OP( 2, lb, sb, 0xffffffffffffffaa, 0, tdat );
   TEST_ST_OP( 3, lb, sb, 0x0000000000000000, 1, tdat );
-#ifdef __RISCVEL
   TEST_ST_OP( 4, lh, sb, 0xffffffffffffefa0, 2, tdat );
-#elif defined(__RISCVEB)
-#else
-  TEST_ST_OP( 4, lh, sb, 0xffffffffffffa0ef, 2, tdat );
-#error unknown endianness!
-#endif
   TEST_ST_OP( 5, lb, sb, 0x000000000000000a, 3, tdat );
 
   # Test with negative offset
@@ -37,23 +31,23 @@ RVTEST_CODE_BEGIN
 
   # Test with a negative base
 
-  TEST_CASE( 10, x3, 0x78, \
+  TEST_CASE( 10, x5, 0x78, \
     la  x1, tdat9; \
     li  x2, 0x12345678; \
     addi x4, x1, -32; \
     sb x2, 32(x4); \
-    lb x3, 0(x1); \
+    lb x5, 0(x1); \
   )
 
   # Test with unaligned base
 
-  TEST_CASE( 11, x3, 0xffffffffffffff98, \
+  TEST_CASE( 11, x5, 0xffffffffffffff98, \
     la  x1, tdat9; \
     li  x2, 0x00003098; \
     addi x1, x1, -6; \
     sb x2, 7(x1); \
     la  x4, tdat10; \
-    lb x3, 0(x4); \
+    lb x5, 0(x4); \
   )
 
   #-------------------------------------------------------------