[rv64ua/lrsc] Initialize memory read out. (#135)

[riscv-tests.git] / isa / rv64ui / sh.S

diff --git a/isa/rv64ui/sh.S b/isa/rv64ui/sh.S
index e68f31af1d19a6e9d7bb6bbe2e05edc5bcdd5ab9..ea9eb2388ff12de8f971e644f49456badb0863e6 100644 (file)
--- a/isa/rv64ui/sh.S
+++ b/isa/rv64ui/sh.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # sh.S
 #-----------------------------------------------------------------------------
@@ -17,13 +19,7 @@ RVTEST_CODE_BEGIN
 
   TEST_ST_OP( 2, lh, sh, 0x00000000000000aa, 0, tdat );
   TEST_ST_OP( 3, lh, sh, 0xffffffffffffaa00, 2, tdat );
-#ifdef __RISCVEL
   TEST_ST_OP( 4, lw, sh, 0xffffffffbeef0aa0, 4, tdat );
-#elif defined(__RISCVEB)
-#else
-  TEST_ST_OP( 4, lw, sh, 0x000000000aa0beef, 4, tdat );
-#error unknown endianness!
-#endif
   TEST_ST_OP( 5, lh, sh, 0xffffffffffffa00a, 6, tdat );
 
   # Test with negative offset
@@ -35,23 +31,23 @@ RVTEST_CODE_BEGIN
 
   # Test with a negative base
 
-  TEST_CASE( 10, x3, 0x5678, \
+  TEST_CASE( 10, x5, 0x5678, \
     la  x1, tdat9; \
     li  x2, 0x12345678; \
     addi x4, x1, -32; \
     sh x2, 32(x4); \
-    lh x3, 0(x1); \
+    lh x5, 0(x1); \
   )
 
   # Test with unaligned base
 
-  TEST_CASE( 11, x3, 0x3098, \
+  TEST_CASE( 11, x5, 0x3098, \
     la  x1, tdat9; \
     li  x2, 0x00003098; \
     addi x1, x1, -5; \
     sh x2, 7(x1); \
     la  x4, tdat10; \
-    lh x3, 0(x4); \
+    lh x5, 0(x4); \
   )
 
   #-------------------------------------------------------------