Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / amoor_w.S

diff --git a/isa/rv64uv/amoor_w.S b/isa/rv64uv/amoor_w.S
index 4d18c1007bb7e48be0237530cb36f144223acf94..db1f2755f48cfa98d11e0c585f0ce2fdd0f81085 100644 (file)
--- a/isa/rv64uv/amoor_w.S
+++ b/isa/rv64uv/amoor_w.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # amoor_w.S
 #-----------------------------------------------------------------------------
@@ -8,11 +10,12 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
+  vsetcfg 4,0
   li a4,2048
-  vvcfgivl a4,a4,4,0
+  vsetvl a4,a4
 
   la a5,amodest
   vmsv vx2,a5
@@ -20,13 +23,13 @@ RVTEST_CODE_BEGIN
   vf %lo(vtcode)(a0)
   la a6,dest
   vsw vx1,a6
-  fence.v.l
+  fence
 
   li a1,0
   li a2,-1
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1