Add another FP recoding test case

[riscv-tests.git] / isa / rv64uv / amoor_w.S

diff --git a/isa/rv64uv/amoor_w.S b/isa/rv64uv/amoor_w.S
index cf8dcbf0299275149b001127be19d2272cb5ef6b..db1f2755f48cfa98d11e0c585f0ce2fdd0f81085 100644 (file)
--- a/isa/rv64uv/amoor_w.S
+++ b/isa/rv64uv/amoor_w.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #*****************************************************************************
 # amoor_w.S
 #-----------------------------------------------------------------------------
@@ -8,13 +10,16 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 4,0
   li a4,2048
   vsetvl a4,a4
 
+  la a5,amodest
+  vmsv vx2,a5
+  lui a0,%hi(vtcode)
   vf %lo(vtcode)(a0)
   la a6,dest
   vsw vx1,a6
@@ -24,7 +29,7 @@ RVTEST_CODE_BEGIN
   li a2,-1
 loop:
   lw a0,0(a6)
-  addi x28,a1,2
+  addi TESTNUM,a1,2
   bne a0,a2,fail
   addi a6,a6,4
   addi a1,a1,1